1. Field of the Invention
The present invention relates to packaging substrates with conductive structure, and more particularly, to a packaging substrate with conductive structure for electrical connection to a chip.
2. Description of Related Art
With existing flip-chip technology, a semiconductor chip is electrically connected to a packaging substrate, wherein electrode pads are provided on the active face (having integrated circuits thereon) of the semiconductor chip, and conductive pads corresponding in position to the electrode pads are provided on the packaging substrate. Soldering structures or other conductive adhesive materials formed between the electrode pads of the semiconductor chip and the conductive pads of the packaging substrate serve as electrical and mechanical connections between the packaging substrate and the semiconductor chip.
As shown in FIG. 1, the flip-chip technology involves forming a plurality of metal bumps 11 on electrode pads 12 of a semiconductor chip 13; forming a pre-soldering structure 14 consisting of a plurality of solders on the conductive pads 15 of a packaging substrate 16; reflowing the pre-soldering structure 14 to the corresponding metal bumps 11 at appropriate reflow temperature to form solder joints 17; and applying an underfill material 18 for coupling the semiconductor chip 13 and the packaging substrate 16 to ensure integrity and reliability of the electrical connection between the semiconductor chip 13 and the packaging substrate 16.
Referring to FIGS. 2A to 2F, a conventional method for fabricating an electrical connection structure of a packaging substrate is illustrated. The method comprises providing a substrate body 20 having a plurality of conductive pads 21 on a surface thereof. In this example, only one conductive pad 21 is shown for simplicity, as shown in FIG. 2A. Then, as shown in FIG. 2B, a solder resist layer 22 is formed on the substrate body 20 and the conductive pad 21. An opening 221 is formed in the solder resist layer 22 for exposing the surface of the conductive pad 21. As shown in FIG. 2C, a stencil 23 covering the substrate body 20 is provided. The stencil 23 has an opening 231 corresponding in position to the conductive pad 21. As shown in FIG. 2D, a stencil printing process is performed to form a soldering material 24 in the opening 231 and the opening 221. As shown in FIG. 2E, the stencil 23 is removed. Finally, as shown in FIG. 2F, the soldering material 24 is reflowed to form a soldering bump 24′, thereby providing electrical connections with the semiconductor chip in a flip-chip manner.
In the above structure applicable to a flip chip package, joints may experience stress caused by the difference in Coefficient of Thermal Expansion (CTE) between the chip and the substrate due to temperature variation during a thermal cycle process of fabrication or when used by users after completion of packaging. As a result, when line width and line pitch of the surface structures of the packaging substrate are reduced, joint strength decreases with joint size, disengagement or cracking of the joint between the soldering bump 24′ and the conductive pad 21 may occur.
Thus, there is a need for a reliable connection structure of the packaging substrate to reduce the occurrence of disengagement or cracking.